Wednesday, June 29, 2011

My Intro to Computer Programming

Zilog Z80


One of the first Z80 microprocessors manufactured; the date stamp is from June 1976.

A CMOS Z80 in a QFP package.
The Zilog Z80 is an 8-bit microprocessor designed by Zilog and sold from July 1976 onwards. It was widely used both in desktop and embedded computer designs as well as for military purposes. The Z80 and its derivatives and clones make up one of the most commonly used CPU families of all time, and, along with the MOS Technology 6502 family, dominated the 8-bit microcomputer market from the late 1970s to the mid-1980s.
Zilog licensed the Z80 design to several vendors, though many East European and Russian manufacturers made unlicensed copies. This enabled a small company's product to gain acceptance in the world market since second sources from far larger companies such as Toshiba started to manufacture the device. Consequently, Zilog has made less than 50% of the Z80s since its conception. In recent decades Zilog has refocused on the ever-growing market for embedded systems (for which the original Z80 and the Z180 were designed) and the most recent Z80-compatible microcontroller family, the fully pipelined 24-bit eZ80 with a linear 16 MB address range, has been successfully introduced alongside the simpler Z180 and Z80 products.
Although Zilog made early attempts with advanced mini-computer-like versions of the Z80-architecture (Z800 and Z280), these chips never caught on. The company was also trying hard in the workstation market with its Z8000 and 32-bit Z80000, both unrelated to the 8-bit Z80.

 Brief history and overview


A May 1976 advertisement for the Zilog Z-80 8-bit microprocessor.

The Z80's original DIL40 chip package pinout.
The Z80 came about when Federico Faggin, after working on the 8080, left Intel at the end of 1974 to found Zilog with Ralph Ungermann, and by July 1976 they had the Z80 on the market.[1] It was designed to be binary compatible with the Intel 8080[2][3] so that most 8080 code, notably the CP/M operating system, would run unmodified on it. Masatoshi Shima, co-designer of the 4004 and the 8080, also contributed to the development of the Z80.[4][5]
The Z80 offered many real improvements over the 8080:[3]
  • An enhanced instruction set[6] including bit manipulation, block move, block I/O, and byte search instructions[7]
  • New IX and IY index registers with instructions for direct base+offset addressing
  • A better interrupt system
    • A more automatic and general vectorized interrupt system, mode 2, as well as a fixed vector interrupt system, mode 1, for simple systems with minimal hardware (mode 0 being the 8080-compatible mode).[8]
    • A non maskable interrupt (NMI) which can be used to respond to power down situations and/or other high priority events (and allowing a minimalistic Z80 system to easily implement a two-level interrupt scheme in mode 1).
    • Two separate register files, which could be quickly switched, to speed up response to interrupts
  • Less hardware required for power supply, clock generation and interface to memory and I/O
    • Single 5 Volt power supply (the 8080 needed -5V/+5V/+12V)
    • Single-phase 5 V clock (the 8080 needed a two-phase high-amplitude clock generator)
    • A built-in DRAM refresh mechanism that would otherwise have to be provided by external circuitry
    • Non-multiplexed buses (the 8080 had state-signals multiplexed onto the data bus)
The Z80 took over from the 8080 and its offspring, the 8085, in the processor market,[9] and became one of the most popular 8-bit CPUs.[10][11] Perhaps a key to the initial success of the Z80 was the built-in DRAM refresh, and other features which allowed systems to be built with fewer support chips (later on, most Z80 systems have been embedded systems, which typically uses static RAM and hence does not need this refresh).
For the original NMOS design, the specified upper clock frequency limit increased successively from the introductory 2.5 MHz, via the well known 4 MHz (Z80A), up to 6 (Z80B) and 8 MHz (Z80H).[12][13] A CMOS version was also developed with specified frequency limits[14] ranging from 4 MHz up to 20 MHz for the version sold today. The CMOS version also allowed a low-power sleep with internal state retained (having no lower frequency limit).[15] The fully compatible derivatives HD64180/Z180[16][17] and eZ80 are currently specified for up to 33 and 50 MHz respectively.

Technical description

Programming model and register set

The programming model and register set are conventional and similar to the related x86 family. The 8080 compatible registers AF, BC, DE, HL are duplicated as two separate banks in the Z80,[18] where the processor can quickly switch from one bank to the other;[19] a feature useful for speeding up responses to single-level, high-priority interrupts. This feature was present in the Datapoint 2200 but was not implemented by Intel in the 8008. The dual-register set makes sense as the Z80 (like most microprocessors at the time) was really intended for embedded use, not for personal computers, or the yet-to-be invented home computers.[20] It also turned out to be quite useful for heavily optimized manual assembly coding. Some software, especially games for the MSX, Sinclair ZX Spectrum and other Z80 based computers took Z80 assembly optimization to rather extreme levels, employing the duplicated registers among other things.

The Z80 architecture.
Registers[21]
Like on the 8080, 8-bit registers are typically coupled to provide 16-bit versions. The 8080 compatible registers are:
  • AF - 8-bit accumulator (A) and flag bits (F) carry, zero, minus, parity/overflow, half-carry (used for BCD), and an Add/Subtract flag (usually called N) also for BCD
  • BC - 16-bit data/address register or two 8-bit registers
  • DE - 16-bit data/address register or two 8-bit registers
  • HL - 16-bit accumulator/address register or two 8-bit registers
  • SP - stack pointer, 16 bits
  • PC - program counter, 16 bits
The new registers introduced with the Z80 are:
  • IX - 16-bit index or base register for 8-bit immediate offsets
  • IY - 16-bit index or base register for 8-bit immediate offsets
  • I - interrupt vector base register, 8 bits
  • R - DRAM refresh counter, 8 bits (msb does not count)
  • AF' - alternate (or shadow) accumulator and flags (toggled in and out with EX AF,AF' )
  • BC', DE', and HL' - alternate (or shadow) registers (toggled in and out with EXX)
  • Four bits of interrupt status and interrupt mode status
There is no direct access to the alternate registers; instead, two special instructions, EX AF,AF' and EXX,[21] each toggles one of two multiplexer flip-flops; this enables fast context switches for interrupt service routines: EX AF, AF' may be used alone (for really simple and fast interrupt routines) or together with EXX to swap the whole AF, BC, DE, HL set; still much faster than pushing the same registers on the stack (slower, lower priority, or multi level interrupts normally use the stack to store registers).
The refresh register, R, increments[22] each time the CPU fetches an opcode (or opcode prefix) and has therefore no simple relationship with program execution. This has sometimes been used to generate pseudorandom numbers in games, and also in software protection schemes. It has also been employed as a "hardware" counter in some designs; a famous example of this is the ZX81, which lets it keep track of character positions on the TV screen by triggering an interrupt at wrap around (by connecting INT to A6).
The interrupt vector register, I, is used for the Z80 specific mode 2 interrupts (selected by the IM 2 instruction). It supplies the high byte of the base address for a 128-entry table of service routine addresses which are selected via a pointer sent to the CPU during an interrupt acknowledge cycle; the low byte of the base address is fixed at zero.[8] The pointer identifies a particular peripheral chip and/or peripheral function or event, where the chips are normally connected in a so called daisy chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively; in interrupt modes 0 and 1 it can be used as simply another 8-bit data register.

 The Z80 assembly language

Background - the Datapoint 2200 and Intel 8008

The first Intel 8008 assembly language was based on a very simple (but systematic) syntax inherited from the Datapoint 2200 design. This original syntax was later transformed into a new, somewhat more traditional, assembly language form for this same original 8008 chip. At about the same time, the new assembly language was also extended to accommodate the added addressing possibilities in the more advanced Intel 8080 chip (the 8008 and 8080 shared a language subset without being binary compatible; the 8008 actually was binary compatible with the Datapoint 2200 however).
In this process, the mnemonic L, for LOAD, was replaced by various abbreviations of the words LOAD, STORE and MOVE, intermixed with other symbolic letters. The mnemonic letter M, for memory (referenced by HL), was lifted out from within the instruction mnemonic to become a syntactically freestanding operand, while registers and combinations of registers became very inconsistently denoted; either by abbreviated operands (MVI D, LXI H etc.), within the instruction mnemonic itself (LDA, LHLD etc.), or both at the same time (LDAX B, STAX D etc.).
Datapoint 2200 & i8008 i8080 Z80 i8086/i8088
ca -1973 ca 1974 1976 1978
LBC MOV B,C LD B,C MOV BL,CL
-- LDAX B LD A,(BC) MOV AL,[BX]
LAM MOV A,M LD A,(HL) MOV AL,[BP]
LBM MOV B,M LD B,(HL) MOV BL,[BP]
-- STAX D LD (DE),A --
LMA MOV M,A LD (HL),A MOV [BP],AL
LMC MOV M,C LD (HL),C MOV [BP],CL
LDI 56 MVI D,56 LD D,56 MOV DL,56
LMI 56 MVI M,56 LD (HL),56 MOV byte ptr [BP],56
-- LDA 1234 LD A,(1234) MOV AL,[1234]
-- STA 1234 LD (1234),A MOV [1234],AL
-- -- LD B,(IX+56) MOV BL,[SI+56]
-- -- LD (IX+56),C MOV [SI+56],CL
-- -- LD (IY+56),78 MOV byte ptr [DI+56],78
-- LXI B,1234 LD BC,1234 MOV BX,1234
-- LXI H,1234 LD HL,1234 MOV BP,1234
-- SHLD 1234 LD (1234),HL MOV [1234],BP
-- LHLD 1234 LD HL,(1234) MOV BP,[1234]
-- -- LD BC,(1234) MOV BX,[1234]
-- -- LD IX,(1234) MOV SI,[1234]
Illustration of four syntaxes, using samples of equivalent, or (for 8086) very similar, load and store instructions.[23]

 The new syntax

Intel had claimed copyright on their assembly mnemonics. Yet another assembly syntax was therefore developed, but this time with a more systematic approach:
  • All registers and register pairs are explicitly denoted by their full names
  • Parentheses are consistently used to indicate "memory contents at" (indirection, or pointer dereferencing) with the exception of some jump instructions.[24]
  • All load and store instructions use the same mnemonic name, LD, for LOAD (a return to the simplistic Datapoint 2200 vocabulary); other common instructions, such as ADD, INC etc., use the same mnemonic regardless of addressing mode or operand size. This is possible because the operands themselves carry enough information.
These principles made it straightforward to find names and forms for all new Z80 instructions, as well as orthogonalizations of old ones, such as LD BC,(1234) above.
It is interesting to see the resemblance between Z80 and 8086 syntax, as illustrated by the table. Apart from naming differences, and despite a certain discrepancy in basic register structure, the two are virtually isomorphous for a large portion of instructions. Whether this is due to some common influence on both design teams (above 8080, such as PDP-11), the competitive nature of the relation between the two designs, or maybe just a matter of taste, is, so far, uncertain.

Instruction set and encoding

The Z80 uses 252 out of the available 256 codes as single byte opcodes ("root instruction"); the four remaining codes are used extensively as opcode prefixes:[26] CB and ED enable extra instructions and DD or FD selects IX+d or IY+d respectively (in some cases without displacement d) in place of HL. This scheme gives the Z80 a large number of permutations of instructions and registers; ZiLOG categorizes these into 158 different "instruction types", 78 of which are the same as those of the Intel 8080[26] (allowing operation of 8080 programs on a Z80). The ZiLOG documentation further groups instructions into the following categories:
  • 8-bit arithmetic and logic operations
  • 16-bit arithmetic
  • 8-bit load
  • 16-bit load
  • Bit set, reset, and test
  • Call, return, and restart
  • Exchange, block transfer, and search
  • General purpose arithmetic and CPU control
  • Input and output
  • Jump
  • Rotate and shift
No multiply instruction is available in the original Z80.[27] Different sizes and variants of additions, shifts, and rotates have somewhat differing effects on flags because the flag-influencing properties of the 8080 were copied. Load instructions do not affect the flags (except for the special purpose I and R register loads). The index register instructions are useful for reducing code size, and, while some of them are not much faster than "equivalent" sequences of simpler operations, they also save execution time indirectly by reducing the need to save and restore registers.[28] Similarly, instructions for 16-bit additions are not particularly fast (11 clocks) in the original Z80; nonetheless, they are about twice as fast as performing the same calculations using 8-bit operations, and equally important, they reduce register usage.

 Undocumented instructions

The index registers, IX and IY, were intended as flexible 16 bit pointers, enhancing the ability to manipulate memory, stack frames and data structures. Officially, they were treated as 16-bit only. In reality, they were implemented as a pair of 8-bit pair registers,[29] in the same fashion as the HL register, which is accessible either as 16 bits or separately as the High and Low registers. Even the binary opcodes (machine language) were identical, but preceded by a new opcode prefix.[30] ZiLOG published the opcodes and related mnemonics for the intended functions, but did not document the fact that every opcode that allowed manipulation of the H and L registers was equally valid for the 8 bit portions of the IX and IY registers. As an example, the opcode 26h followed by an immediate byte value (LD H,n) will load that value into the H register. Preceding this two-byte instruction with the IX register's opcode prefix DD, would instead result in the most significant 8 bits of the IX register being loaded with that same value. A notable exception to this would be instructions similar to LD H,(IX+d) which make use of both the HL and IX or IY registers in the same instruction;[30] in this case the DD prefix is only applied to the (IX+d) portion of the instruction.
There are several other undocumented instructions as well.[31]

 Instruction execution

Each instruction is executed in steps that are usually termed machine cycles (M-cycles), each of which can take between three and six clock periods (T-cycles).[32] Each M-cycle corresponds roughly to one memory access and/or internal operation. Many instructions actually end during the M1 of the next instruction which is known as a fetch/execute overlap.
Examples of typical instructions (R=read, W=write)
Total M-cycles instruction M1 M2 M3 M4 M5 M6
1[33] INC BC opcode




2[34] ADD A,n opcode n



3[35] ADD HL,DE opcode internal internal


4[36] SET b,(HL) prefix opcode R(HL), set W(HL)

5[37] LD (IX+d),n prefix opcode d n,add W(IX+d)
6[38] INC (IY+d) prefix opcode d add R(IY+d),inc W(IY+d)
The Z80 machine cycles are sequenced by an internal state machine which builds each M-cycle out of 3, 4, 5 or 6 T-cycles depending on context. This avoids cumbersome asynchronous logic and makes the control signals behave consistently at a wide range of clock frequencies. Naturally, it also means that a higher frequency crystal must be used than without this subdivision of machine cycles (approximately 2–3 times higher). It does not imply tighter requirements on memory access times, however, as a high resolution clock allows more precise control of memory timings and memory therefore can be active in parallel with the CPU to a greater extent (i.e. sitting less idle), allowing more efficient use of available memory performance. For instruction execution, the Z80 combines two full clock cycles into a long memory access period (the M1-signal) which would typically last only a fraction of a (longer) clock cycle in a more asynchronous design (such as the 6800, or similar).
Memory, especially EPROM, but also Flash, were generally slow as compared to the state machine sub-cycles (clock cycles) used in contemporary microprocessors. The shortest machine cycle that could safely be used in embedded designs has therefore often been limited by memory access times, not by the maximum CPU frequency (especially so during the home computer era). However, this relation has slowly changed during the last decades, particularly regarding SRAM; cacheless, single-cycle designs such as the eZ80 have therefore become much more meaningful recently.

Compatible peripherals

Zilog introduced a number of peripheral parts for the Z80, which all supported the Z80's interrupt handling system and I/O address space. These included the CTC (Counter-Timer-Circuit), the SIO (Serial Input Output), the DMA (Direct Memory Access), the PIO (Parallel Input-Output) and the DART (Dual Asynchronous Receiver Transmitter). As the product line developed, low-power, high-speed and CMOS versions of these chips were produced.
Like the 8080, 8085 and 8086 processors, but unlike processors such as the Motorola 6800 and MOS Technology 6502, the Z80 and 8080 had a separate control line and address space for I/O instructions. While some Z80-based computers used "Motorola-style" memory mapped input/output devices, usually the I/O space was used to address one of the many Zilog peripheral chips compatible with the Z80. Zilog I/O chips supported the Z80's new mode 2 interrupts (see description above) which simplified interrupt handling for large numbers of peripherals.

'Undocumented' 16 bit I/O-addressing

The Z80 was officially described as supporting 16-bit (64 KB) memory addressing, and 8-bit (256 ports) I/O-addressing. Looking carefully at the hardware reference manual, it can be seen that all I/O instructions actually assert the entire 16-bit address bus. OUT (C),reg and IN reg,(C) places the contents of the entire 16 bit BC register on the address bus;[39] OUT (n),A and IN A,(n) places the contents of the A register on b8-b15 of the address bus and n on b0-b7 of the address bus. A designer could choose to decode the entire 16 bit address bus on I/O operations in order to take advantage of this feature, or use the high half of the address bus to select subfeatures of the I/O device. This feature has also been used to minimise decoding hardware requirements, such as in the Amstrad CPC and ZX81.


NEC's μPD780C Z80 clone.

Sharp's LH0080A Z80 clone

The T34BM1, a Russian Z80 clone.

Toshiba TMPZ84C015; a standard Z80 with several Z80-family peripherals on chip in a QFP package.

The Z80 compatible Hitachi HD64180.

Z180 in a PLCC package.

The Z80 compatible R800 in QFP.

The Z280 in a PLCC package
Mostek MK3880 and SGS-Thomson Z8400 (now STMicroelectronics) were both second-sources for the Z80. Sharp and NEC developed clones in NMOS, the LH0080 and µPD780C respectively. Toshiba made a CMOS-version, the TMPZ84C00, which is believed[by whom?] (but not verified) to be the same design also used by Zilog for its own CMOS Z84C00. There were also Z80-chips made by GoldStar (alias LG) and the BU18400 series of Z80-clones (including DMA, PIO, CTC, DART and SIO) in NMOS and CMOS made by ROHM Electronics.
In East Germany, an unlicensed clone of the Z80, known as the U880, was manufactured. It was very popular and was used in Robotron's and VEB Mikroelektronik Mühlhausen's computer systems (e.g. the KC85-series) and also in many self-made computer systems (ex. COMP JU+TER). In Romania another unlicensed clone could be found, named MMN80CPU and produced by Microelectronica, used in home computers like TIM-S, HC, COBRA.
Also, several clones of Z80 were created in the Soviet Union, notable ones being the T34BM1, also called КP1858ВМ1 (parallelling the Russian 8080-clone KR580VM80A) The first marking was used in pre-production series, while the second had to be used for a larger production. Though, due to the collapse of Soviet microelectronics in late 80s, there are many more T34BM1s than КP1858ВМ1s.

Derivatives

Compatible with the original Z80
  • Hitachi developed the HD64180, a microcoded and partially dynamic Z80 in CMOS, with on chip peripherals and a simple MMU giving a 1 MB address space. It was later second sourced by Zilog, initially as the Z64180, and then in the form of the slightly modified Z180[40] which has bus protocol and timings better adapted to Z80 peripheral chips. Z180 has been maintained and further developed under Zilog's name, the newest versions being based on the fully static S180/L180 core with very low power draw and EMI (noise).
  • Toshiba developed the 84 pin Z84013 / Z84C13 and the 100 pin Z84015 / Z84C15 series of "intelligent peripheral controllers", basically ordinary NMOS and CMOS Z80 cores with Z80 peripherals, watch dog timer, power on reset, and wait state generator on the same chip. Manufactured by Sharp as well as Toshiba. These products are today second sourced by Zilog.[41]
  • The 32-bit Z80 compatible Zilog Z380, introduced 1994, has survived but never gained real momentum; it is used mainly in telecom equipment.
  • Zilog's fully pipelined Z80 compatible eZ80[42] with an 8/16/24-bit word length and a linear 16 MB address space was introduced in 2001. It exists in versions with on chip SRAM and/or flash memory, as well as with integrated peripherals. One variant has on chip MAC (media access controller), and available software include a TCP/IP stack. In contrast with the Z800 and Z280, there are only a few added instructions (primarily LEAs, PEAs, and variable-address 16/24-bit loads), but instructions are instead executed between 2 and 11 times as clock cycle efficient as on the original Z80 (with a mean value around 3-5 times). It is currently specified for clock frequencies up to 50 MHz.
  • Kawasaki developed the binary compatible KL5C8400 which is approximately 1.2-1.3 times as clock cycle efficient as the original Z80 and can be clocked at up to 33 MHz. Kawasaki also produces the KL5C80A1x family, which has peripherals as well as a small RAM on chip; it is approximately as clock cycle efficient as the eZ80 and can be clocked at up to 10 MHz (2006).[43]
  • The Chinese Actions Semiconductor's audio processor family of chips (ATJ2085 and others) contains a Z80-compatible MCU together with a 24-bit dedicated DSP processor.[44] These chips are used in many MP3 and media player products.
Non-compatible
  • The Toshiba TLCS 900 series of high volume (mostly OTP) microcontrollers are based on the Z80; they share the same basic BC,DE,HL,IX,IY register structure, and largely the same instructions, but are not binary compatible, while the previous TLCS 90 is Z80-compatible.[45]
  • The NEC 78K series microcontrollers are based on the Z80; they share the same basic BC,DE,HL register structure, and has similar (but differently named) instructions; not binary compatible.
Partly compatible
No longer produced:
  • The ASCII Corporation R800 was a fast 16-bit processor used in MSX TurboR computers; it was software, but not hardware compatible with the Z80 (signal timing, pinout & function of pins differ from the Z80).
  • Zilog's ill-fated NMOS Z800 and CMOS Z280 were quite fast Z80-implementations (before the HD64180 / Z180) with a 16 MB paged MMU address space; they added many orthogonalizations and addressing modes to the Z80 instruction set, but were too complex and mini-computer inspired to be a natural choice for most embedded applications.[48] In contrast, the plain CMOS Z80 has remained popular, alongside the compatible Z180 and eZ80 families.

 FPGA and ASIC versions

A commercial, functionally equivalent, CPU core is the Evatronix CZ80CPU,[49] available as synthesizable VHDL or Verilog source code, for high-volume ASICs, or as post-synthesis EDIF netlists, for low-volume FPGAs from Actel, Altera, Lattice or Xilinx.
Free versions are the T80 and TV80, available as VHDL and Verilog sources under a BSD style license.[50][51][52] The VHDL version, once synthesized, can be clocked up to 35 MHz on a Xilinx Spartan II FPGA. For large production series, it is much cheaper to use a traditional solution (or ASIC) than an FPGA, however.

 Software emulation

Software emulation of the Z80 instruction set on modern PCs runs faster than the original Z80 CPU ran and is used for home computer simulators (such as Amstrad CPC, MSX and Sinclair ZX Spectrum) and also for video game emulators such as MAME, which executes arcade video games. SIMH emulates MITS Altair 8800 computer with Intel 8080, Zilog Z80 or Intel 8086 processors.


In desktop computers

For a comprehensive overview, see the List of home computers using the Z80.
During the late 1970s and early 1980s, the Z80 was used in a great number of fairly anonymous business-oriented machines with the CP/M operating system, a combination that dominated the market at the time.[53][54]
Two well-known examples of Z80+CP/M business computers are the portable Osborne 1 and the Kaypro series. Research Machines manufactured the 380Z and 480Z microcomputers which were networked with a thin Ethernet type LAN and CP/NET in 1981. Other manufacturers of such systems included Televideo, Xerox (820 range) and a number of more obscure firms. Some systems used multi-tasking operating system software to share the one processor between several concurrent users.
The Radio Shack TRS-80, introduced in 1977, used the Z80, as did the follow on Models II,III,IV and proposed Model V. In the United Kingdom, Sinclair Research used the Z80 and Z80A in its ZX80, ZX81 and ZX Spectrum home computers, and Amstrad used them in their Amstrad CPC line.
The Commodore 128 featured a Z80 processor alongside its MOS Technology 8502 processor for CP/M compatibility.[55] Other 6502 architecture computers on the market at the time, such as the BBC Micro, Apple II[56] and the 6510 based Commodore 64,[57] could make use of the Z80 with an external unit, a plug-in card, or an expansion cartridge. The Microsoft Z-80 SoftCard for the Apple II was a particularly successful add-on card and one of Microsoft's few hardware products of the era.
The Acer company, formerly Multitech, introduced the Microprofessor I, in 1981. It was designed as a simple and inexpensive training system for the Z80 microprocessor. Currently, it is still being manufactured and sold by Flite Electronics International Limited in Southampton, England

 In embedded systems and consumer electronics


Z80 based PABX. The Z80 is to the right of the chip which has a label stuck on.
The Zilog Z80 has long been a popular microprocessor in embedded systems and microcontroller cores,[21] where it remains in widespread use today.[10][58] The following list provides examples of such applications of the Z80, including uses in consumer electronics products.

 Industrial/professional

Consumer electronics

Musical instruments, etc.

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